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| CY7C1069DV33 16-Mbit (2M x 8) Static RAM Features Functional Description The CY7C1069DV33 is a high performance CMOS Static RAM organized as 2,097,152 words by 8 bits. To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A20). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the IO pins. See Truth Table on page 8 for a complete description of Read and Write modes. The input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C1069DV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and a 48-Ball very fine pitch ball grid array (VFBGA) package. High speed tAA = 10 ns Low active power ICC = 175 mA at 10 ns Low CMOS standby power ISB2 = 25 mA Operating voltages of 3.3 0.3V 2.0V data retention Automatic power down when deselected TTL compatible inputs and outputs Easy memory expansion with CE1 and CE2 features Available in Pb-free 54-Pin TSOP II and 48-Ball VFBGA packages Logic Block Diagram INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER SENSE AMPS 2M x 8 ARRAY IO0 - IO7 COLUMN DECODER WE CE2 OE CE1 Cypress Semiconductor Corporation Document Number: 38-05478 Rev. *D * A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19 A20 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised September 06, 2007 CY7C1069DV33 Selection Guide -10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 175 25 Unit ns mA mA Pin Configuration Figure 1. 54-Pin TSOP II (Top View) [1] Figure 2. 48-Ball VFBGA (Top View) [1] NC VCC NC IO6 VSS IO7 A4 A3 A2 A1 A0 NC CE1 VCC WE CE2 A19 A18 A17 A16 A15 IO0 VCC IO1 NC VSS NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 NC VSS NC IO5 VCC IO4 A5 A6 A7 A8 A9 NC OE VSS NC A20 A10 A11 A12 A13 A14 IO3 VSS IO2 NC VCC NC 1 NC NC IO0 VSS VCC IO3 NC A19 2 OE NC NC IO1 IO2 NC NC A8 3 A0 A3 A5 A17 A18 A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 NC IO5 IO6 NC WE A11 6 CE2 NC IO4 VCC VSS IO7 NC A20 A B C D E F G H Note 1. NC pins are not connected on the die. Document Number: 38-05478 Rev. *D Page 2 of 10 CY7C1069DV33 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage on VCC Relative to GND [2] ....-0.5V to +4.6V DC Voltage Applied to Outputs in High Z State [2] ................................... -0.5V to VCC + 0.5V DC Input Voltage [2] ............................... -0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............. ...............................>2001V (MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA Operating Range Range Industrial Ambient Temperature -40C to +85C VCC 3.3V 0.3V DC Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage [2] Test Conditions VCC = Min, IOH = -4.0 mA VCC = Min, IOL = 8.0 mA -10 Min 2.4 0.4 2.0 -0.3 VCC + 0.3 0.8 +1 +1 175 30 25 Max Unit V V V V A A mA mA mA Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VOUT < VCC, Output disabled VCC = Max, f = fMAX = 1/tRC, IOUT = 0 mA CMOS levels -1 -1 Automatic CE Power Down Max VCC, CE1 > VIH, CE2 < VIL, Current -- TTL Inputs VIN > VIH or VIN < VIL, f = fMAX Automatic CE Power Down Max VCC, CE1 > VCC - 0.3V, CE2 < 0.3V, Current --CMOS Inputs VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Note 2. VIL (min) = -2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. Document Number: 38-05478 Rev. *D Page 3 of 10 CY7C1069DV33 Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance IO Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V TSOP II 6 8 VFBGA 8 10 Unit pF pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still air, soldered on a 3 x 4.5 inch, four layer printed circuit board TSOP II 24.18 5.40 VFBGA 28.37 5.79 Unit C/W C/W AC Test Loads and Waveforms The AC test loads and waveform diagram follows. [3] High-Z characteristics 3.3V OUTPUT 5 pF* 3.0V GND Rise Time > 1 V/ns ALL INPUT PULSES 90% 10% 90% 10% INCLUDING JIG AND SCOPE (b) R2 351 50 OUTPUT Z0 = 50 30 pF* VTH = 1.5V R1 317 (a) * Capacitive load consists of all components of the test environment (c) Fall Time: > 1 V/ns Note 3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100 s (tpower) after reaching the minimum operating VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. Document Number: 38-05478 Rev. *D Page 4 of 10 CY7C1069DV33 AC Switching Characteristics Over the Operating Range [4] Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle [8, 9] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write Cycle Time CE1 LOW/CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High Z [6] [6] Description -10 Min 100 10 10 3 10 5 1 5 3 5 Max Unit VCC(Typical) to the First Access [5] Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW/CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z [6] s ns ns ns ns ns ns ns ns ns ns 10 ns ns ns ns ns ns ns ns ns ns 5 ns CE1 LOW/CE2 HIGH to Low Z [6] CE1 HIGH/CE2 LOW to High Z [6] [7] [7] CE1 LOW/CE2 HIGH to Power Up 0 CE1 HIGH/CE2 LOW to Power Down 10 7 7 0 0 7 5.5 0 3 Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading shown in part a) of AC Test Loads and Waveforms, unless specified otherwise. 5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 6. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured 200 mV from steady state voltage. 7. These parameters are guaranteed by design and are not tested. 8. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. CE1 and WE are LOW along with CE2 HIGH to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05478 Rev. *D Page 5 of 10 CY7C1069DV33 Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR [10] tR [ 11] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions VCC = 2V , CE1 > VCC - 0.2V, CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V Min 2 Typ Max 25 Unit V mA ns ns 0 tRC Data Retention Waveform DATA RETENTION MODE VCC CE 3.0V tCDR VDR > 2V 3.0V tR Switching Waveforms Figure 3. Read Cycle No. 1 [12, 13] tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled) [13, 15] ADDRESS tRC CE1 CE2 tACE OE tDOE tLZOE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE ICC ISB Notes 10. Tested initially and after any design or process changes that may affect these parameters. 11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 12. The device is continuously selected. CE1 = VIL, and CE2 = VIH. 13. WE is HIGH for read cycle. 14. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH. Document Number: 38-05478 Rev. *D Page 6 of 10 CY7C1069DV33 Switching Waveforms (continued) Figure 5. Write Cycle No. 1 (CE Controlled) [15, 16, 17] tWC ADDRESS CE tSA tSCE tAW tPWE WE tSD DATA IO tHD tHA Figure 6. Write Cycle No. 2 (WE Controlled, OE LOW) [15, 16, 17] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA tHZWE DATA IO tSD tHD tLZWE Notes 15. CE is a shorthand combination of both CE1 and CE2 combined. It is active LOW. 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 38-05478 Rev. *D Page 7 of 10 CY7C1069DV33 Truth Table CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H IO0 - IO7 High Z High Z Data Out Data In High Z Power Down Power Down Read All Bits Write All Bits Selected, Outputs Disabled Mode Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Power Ordering Information Speed (ns) 10 Ordering Code CY7C1069DV33-10ZSXI CY7C1069DV33-10BVXI Package Diagram Package Type Operating Range Industrial 51-85160 54-Pin TSOP II (Pb-Free) 51-85178 48-Ball VFBGA (8 x 9.5 x 1 mm) (Pb-Free) Package Diagrams Figure 7. 54-Pin TSOP Type II 51-85160-** Document Number: 38-05478 Rev. *D Page 8 of 10 CY7C1069DV33 Package Diagrams (continued) Figure 8. 48-Ball VFBGA (8 x 9.5 x 1 mm) BOTTOM VIEW TOP VIEW O0.05 M A1 CORNER 12 3 4 5 6 C A1 CORNER O0.25 M C A B O0.300.05(48X) 6 54 3 2 1 A B C E F G H A B C D E 9.500.10 5.25 D 9.500.10 0.75 2.625 F G H A B 8.000.10 A 1.875 0.75 3.75 0.55 MAX. 0.25 C 0.210.05 B 8.000.10 0.10 C 0.15(4X) SEATING PLANE 0.26 MAX. C 1.00 MAX 51-85178. ** Document Number: 38-05478 Rev. *D Page 9 of 10 CY7C1069DV33 Document History Page Document Title: CY7C1069DV33 16-Mbit (2M x 8) Static RAM Document Number: 38-05478 REV. ** *A *B ECN NO. 201560 233748 469420 Issue Date See ECN See ECN See ECN Orig. of Change SWI RKF NXR Advance datasheet for C9 IPP Modified AC, DC parameters as per EROS (Specification 01-2165) Pb-free Offering in the Ordering Information Converted from Advance Information to Preliminary Removed -8 and -12 speed bins from product offering Removed Commercial Operating Range Changed 2G Ball of FBGA and pin 40 of TSOPII from DNU to NC Included the Maximum ratings for Static Discharge Voltage and Latch Up Current on page 3 Changed ICC(Max) from 220 mA to 100 mA Changed ISB1(Max) from 70 mA to 30 mA Changed ISB2(Max) from 40 mA to 25 mA Specified the Overshoot specification in footnote 1 Added Data Retention Characteristics table on page 5 Updated the 48-pin FBGA package Updated the Ordering Information table. Added note 1 for NC pins Updated Test Condition for ICC in DC Electrical Characteristics table Updated the 48-Ball FBGA Package Description of Change *C 499604 See ECN NXR *D 1462585 See ECN VKN/AESA Converted from preliminary to final Changed ICC spec from 125 mA to 175 mA Updated thermal specs (c) Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05478 Rev. *D Revised September 06, 2007 Page 10 of 10 All product and company names mentioned in this document are the trademarks of their respective holders. |
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